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ICS9E4101 idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 programmable timing control hub tm for intel systems 1 datasheet pin configuration recommended application: i-temp ck410 clock, intel yellow cover part output features: ? 2 - 0.7v current-mode differential cpu pairs 6 - 0.7v current-mode differential src pair for sata and pci-e 1 - 0.7v current-mode differential cpu/src selectable pair 6 - pci (33mhz) 3 - pciclk_f, (33mhz) free-running 1 - usb, 48mhz 1 - dot, 96mhz, 0.7v current differential pair 1 - ref, 14.318mhz key specifications: cpu outputs cycle-cycle jitter < 85ps src output cycle-cycle jitter <125ps pci outputs cycle-cycle jitter < 500ps +/- 300ppm frequency accuracy on cpu & src clocks features/benefits: supports tight ppm accuracy clocks for serial-ata and pci-express supports spread spectrum modulation, 0 to -0.5% down spread supports cpu clks up to 400mhz uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning supports undriven differential cpu, src pair in pd# for power management. 56-pin ssop vddpci 1 56 pciclk2 gnd 2 55 pciclk1 pciclk3 3 54 pciclk0 pciclk4 4 53 fs_c/test_sel pciclk5 5 52 refout gnd 6 51 gnd vddpci 7 50 x1 itp_en/pciclk_f0 8 49 x2 pciclk_f1 9 48 vddref pciclk_f2 10 47 sdata vdd48 11 46 sclk usb_48mhz 12 45 gnd gnd 13 44 cpuclkt0 dott_96mhz 14 43 cpuclkc0 dotc_96mhz 15 42 vddcpu fs_b/test_mode 16 41 cpuclkt1 vtt_pwrgd#/pd 17 40 cpuclkc1 fs_a_410 18 39 iref srcclkt1 19 38 gnda srcclkc1 20 37 vdda vddsrc 21 36 cpuclkt2_itp/srcclkt_7 srcclkt2 22 35 cpuclkc2_itp/srcclkc_7 srcclkc2 23 34 vddsrc srcclkt3 24 33 srcclkt6 srcclkc3 25 32 srcclkc6 srcclkt4_sata 26 31 srcclkt5 srcclkc4_sata 27 30 srcclkc5 vddsrc 28 29 gnd ICS9E4101 functionality fs_c 1 fs_b 2 fs_a 2 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 011 100 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 110 111 1. fs_c is a three-level input. please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs_b and fs_a are low-threshold inputs. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. reserved reserved reserved reserved
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 2 pin description pin # pin name pin type description 1 vddpci pwr power supply for pci clocks, nominal 3.3v 2 gnd pwr ground pin. 3 pciclk3 out pci clock output. 4 pciclk4 out pci clock output. 5 pciclk5 out pci clock output. 6 gnd pwr ground pin. 7 vddpci pwr power supply for pci clocks, nominal 3.3v 8 itp_en/pciclk_f0 i/o free running pci clock not affected by pci_stop#. itp_en: latched input to select pin functionality 1 = cpu_itp pair 0 = src pair 9 pciclk_f1 out free running pci clock not affected by pci_stop# . 10 pciclk_f2 out free running pci clock not affected by pci_stop# . 11 vdd48 pwr power pin for the 48mhz output.3.3v 12 usb_48mhz out 48.00mhz usb clock 13 gnd pwr ground pin. 14 dott_96mhz out true clock of differential pair for 96.00mhz dot clock. 15 dotc_96mhz out complement clock of differential pair for 96.00mhz dot clock. 16 fs_b/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 17 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks, plls and the crystal oscillator are stopped. 18 fs_a_410 in 3.3v tolerant low threshold input for cpu frequency selection. this pin requires ck410 fsa. refer to input electrical characteristics for vil_fs and vih_fs threshold values. 19 srcclkt1 out true clock of differential src clock pair. 20 srcclkc1 out complement clock of differential src clock pair. 21 vddsrc pwr supply for src clocks, 3.3v nominal 22 srcclkt2 out true clock of differential src clock pair. 23 srcclkc2 out complement clock of differential src clock pair. 24 srcclkt3 out true clock of differential src clock pair. 25 srcclkc3 out complement clock of differential src clock pair. 26 srcclkt4_sata out true clock of differential src/sata pair. 27 srcclkc4_sata out complement clock of differential src/sata pair. 28 vddsrc pwr supply for src clocks, 3.3v nominal
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 3 pin description (continued) pin # pin name type description 29 gnd pwr ground pin. 30 srcclkc5 out complement clock of differential src clock pair. 31 srcclkt5 out true clock of differential src clock pair. 32 srcclkc6 out complement clock of differential src clock pair. 33 srcclkt6 out true clock of differential src clock pair. 34 vddsrc pwr supply for src clo cks, 3.3v nominal 35 cpuclkc2_itp/srcclkc_7 out complimentary clock of cpu_itp/src differential pair cpu_itp/src output. these are current mode outputs. external resistors are required for voltage bias. selected by itp_en input. 36 cpuclkt2_itp/srcclkt_7 out true clock of cpu_itp/src differential pair cpu_itp/src output. these are current mode outputs. external resistors are required for voltage bias. selected by itp_en input. 37 vdda pwr 3.3v power for the pll core. 38 gnda pwr ground pin for the pll core. 39 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 40 cpuclkc1 out complimentary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 42 vddcpu pwr supply for cpu clo cks, 3.3v nominal 43 cpuclkc0 out complimentary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 44 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 45 gnd pwr ground pin. 46 sclk in clock pin of smbus circuitry, 5v tolerant. 47 sdata i/o data pin for smbus circuitry, 5v tolerant. 48 vddref pwr ref, xtal power supply, nominal 3.3v 49 x2 out crystal output, nominally 14.318mhz 50 x1 in crystal input, nominally 14.318mhz. 51 gnd pwr ground pin. 52 refout out reference clock output 53 fs_c/test_sel in 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values. test_sel: 3-level latched input to enable test mode. refer to test clarification table 54 pciclk0 out pci clock output. 55 pciclk1 out pci clock output. 56 pciclk2 out pci clock output.
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 4 general description block diagram power groups ICS9E4101 follows intel ck410 yellow cover specification. this clock synthesizer provides a single chip solution for next generation p4 intel processors and intel chipsets. ICS9E4101 is driven with a 14.318mhz crystal. it generates cpu outputs up to 400mhz. it also provides a tight ppm accuracy output for serial ata and pci-express support. i ref pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz, usb x1 x2 xtal sdata sclk v tt_pwrgd#/pd fs_a fs_b fs_c itp_en test_mode test_sel control logic refout cpuclkt (2:0) cpuclkc (2:0) srcclkt (7:1) srcclkc (7:1) pciclk (5:0) pciclkf (2:0) 96mhz_dott_0 96mhz_dotc_0 vdd gnd 48 51 xtal, ref 1,7 2,6 pciclk outputs 21,28,34 29 srcclk outputs 37 38 master clock, cpu analog 11 13 dot, usb, pll_48 42 45 cpuclk clocks description pin number
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 5 general i 2 c serial interface information for the ICS9E4101 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 6 i 2 c table: read-back register pin # nam e control function t yp e0 1 pwd bit 7 cpuclk2/rcclk7 e nable output enable rw disable enable 1 bit 6 srcclk6 enable output enable rw disable enable 1 bit 5 srcclk5 enable output enable rw disable enable 1 bit 4 srcclk4 enable output enable rw disable enable 1 bit 3 srcclk3 enable output enable rw disable enable 1 bit 2 srcclk2 enable output enable rw disable enable 1 bit 1 srcclk1 enable output enable rw disable enable 1 bit 0 i 2 c table: spreading and device behavior control register pin # nam e control function t yp e0 1 pwd bit 7 pci_f0 enable output enable rw disable enable 1 bit 6 dot_96mhz output enable rw disable enable 1 bit 5 usb_48mhz enable output enable rw disable enable 1 bit 4 refout enable output enable rw disable enable 1 bit 3 1 bit 2 cput1/cpuc1 output enable rw disable enable 1 bit 1 cput0/cpuc0 output enable rw disable enable 1 bit 0 spread spectrum mode spread off rw spread off spread on 0 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 pciclk5 output enable rw disable enable 1 bit 6 pciclk4 output enable rw disable enable 1 bit 5 pciclk3 out p ut enable rw disable enable 1 bit 4 pciclk2 out p ut enable rw disable enable 1 bit 3 pciclk1 out p ut enable rw disable enable 1 bit 2 pciclk0 output enable rw disable enable 1 bit 1 pci_f2 enable output enable rw disable enable 1 bit 0 pci_f1 enable output enable rw disable enable 1 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 cpu_itp/srcclk7 rw free-running stoppable 0 bit 6 srcclk6 rw free-running stoppable 0 bit 5 srcclk5 rw free-runnin g stoppable 0 bit 4 srcclk4 rw free-running stoppable 0 bit 3 srcclk3 rw free-runnin g stoppable 0 bit 2 srcclk2 rw free-running stoppable 0 bit 1 srcclk1 rw free-runnin g stoppable 0 bit 0 0 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 1 bit 6 dot_96mhz driven in pd rw driven hi-z 1 bit 5 pci_f2 rw free-running stoppable 1 bit 4 pci_f1 rw free-runnin g stoppable 1 bit 3 pci_f0 rw free-running stoppable 1 bit 2 1 bit 1 1 bit 0 1 free-running control default: not affected by pci/src_stop (byte 6, bit 3) reserved reserved - b y te 1 54 14,15 reserved 35,35 12 52 14,15 b y te 3 43,44 - 40,41 b y te 2 5 10 reserved 24,25 22,23 19,20 b y te 4 - 26,27 24,25 22,23 19,20 b y te 0 35,36 32,33 30,31 10 9 8 reserved reserved free-running control not affected by reserved 4 3 56 55 30,31 26,27 32,33 9 54
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 7 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 src stop drive mode drive mode in pci_stop rw driven hi-z 0 bit 6 0 bit 5 0 bit 4 0 bit 3 src pd drive mode drive mode in pd rw driven hi-z 0 bit 2 cpuclk_itp drive mode in pd rw driven hi-z 0 bit 1 cpuclk1 drive mode in pd rw driven hi-z 0 bit 0 cpuclk0 drive mode in pd rw driven hi-z 0 i 2 c table: output control register pin # nam e control function t yp e0 1 pwd bit 7 test mode selection test mode selection rw hi-z ref/n 0 bit 6 test clock mode entry test mode rw disable enable 0 bit 5 0 bit 4 refout stren g th stren g th pro g rw 1x 2x 1 bit 3 pci/src_stop stop all pci and src clocks rw enabled, all stoppable pci and src clocks are stopped. disabled, all stoppable pci and src clo cks are running 1 bit 2 fs_ c readback r - - latched bit 1 fs_b readback r - - latched bit 0 fs_a readback r - - latched i 2 c table: vendor & revision id register pin # nam e control function t yp e0 1 pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 i 2 c table: byte count register pin # nam e control function t yp e0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 0 bit 1 bc1 rw - - 0 bit 0 bc0 rw - - 0 - - b y te 5 b y te 6 19,20,22,23, 24,25,26,27,30,31, 32,33,35,36 reserved reserved 17,18,19,20,22,23, 24,25,26,27,30,31, 32,33,35,36 54,55,56,3,4,5,8,9, 10 19,20,22,23, 24,25,26,27,30,31, 32,33,35,36 35,36 revision id reserved - - 40,41 43,44 52 - - - - - reserved - vendor id - - - b y te 7 - b y te 8 - - - - writing to this register will configure how many bytes will be read back, default is 08 = 8 bytes. - - - -
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 8 i 2 c table: watchdog timer register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 wd4 rw - - 0 bit 3 wd3 rw - - 0 bit 2 wd2 rw - - 0 bit 1 wd1 rw - - 0 bit 0 wd0 rw - - 0 pin # nam e control function t yp e0 1 pwd bit 6 wden watchdog enable r disable enable 1 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 i 2 c table: vco frequency control register pin # nam e control function t yp e0 1 pwd bit 7 n div8 n divider bit 8 rw - - x bit 6 m div6 rw - - x bit 5 m div5 rw - - x bit 4 m div4 rw - - x bit 3 m div3 rw - - x bit 2 m div2 rw - - x bit 1 m div1 rw - - x bit 0 m div0 rw - - x i 2 c table: vco frequency control register pin # nam e control function t yp e0 1 pwd bit 7 n div7 rw - - x bit 6 n div6 rw - - x bit 5 n div5 rw - - x bit 4 n div4 rw - - x bit 3 n div3 rw - - x bit 2 n div2 rw - - x bit 1 n div1 rw - - x bit 0 n div0 rw - - x i 2 c table: spread spectrum control register pin # nam e control function t yp e0 1 pwd bit 7 ssp7 rw - - x bit 6 ssp6 rw - - x bit 5 ssp5 rw - - x bit 4 ssp4 rw - - x bit 3 ssp3 rw - - x bit 2 ssp2 rw - - x bit 1 ssp1 rw - - x bit 0 ssp0 rw - - x 0 m/nen m/n programming enable rw disable - enables prograaming bytes 10-19 b y te 9 - - - - - - i 2 c table: vco control select bit & wd timer control re g ister b y te 10 bit 7 the decimal representation of m div (6:0) is equal to reference divider value. default at power up = latch-in or byte 0 rom b y te 11 - - - - - - - - the decimal representation of n div (8:0) is equal to vco divider value. default at power up = latch-in or byte 0 rom table. b y te 12 - - - - - - - - these spread spectrum bits will program the spread pecentage. it is recommended to use ics spread % table for spread pro g rammin g . b y te 13 - - - - - - - - reserved reserved reserved reserved enable reserved reserved reserved reserved reserved
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 9 i 2 c table: spread spectrum control register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 ssp13 rw - - x bit 4 ssp12 rw - - x bit 3 ssp11 rw - - x bit 2 ssp10 rw - - x bit 1 ssp9 rw - - x bit 0 ssp8 rw - - x i 2 c table: out p ut divider control re g ister pin # nam e control function t yp e0 1 pwd bit 7 src div3 rw x bit 6 src div2 rw x bit 5 src div1 rw x bit 4 src div0 rw x bit 3 cpu div3 rw x bit 2 cpu div2 rw x bit 1 cpu div1 rw x bit 0 cpu div0 rw x i 2 c table: out p ut divider control re g ister pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 pci div3 rw x bit 2 pci div2 rw x bit 1 pci div1 rw x bit 0 pci div0 rw x i 2 c table: vendor & revision id register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 pciinv pci phase invert rw default inverse 0 bit 5 srcinv src phase invert rw default inverse 0 bit 4 cpuinv cpu phase invert rw default inverse 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 i 2 c table: group skew control register pin # nam e control function t yp e0 1 pwd bit 7 src_skw3 rw 0 bit 6 src_skw2 rw 0 bit 5 src_skw1 rw 0 bit 4 src_skw0 rw 0 bit 3 cpu_skw3 rw 0 bit 2 cpu_skw2 rw 0 bit 1 cpu_skw1 rw 0 bit 0 cpu_skw0 rw 0 src skew control cpu skew control - - - it is recommended to use ics spread % table for spread programming. b y te 14 - - - - - - b y te 15 - src divider ratio can be configured via these 4 bits individually. - - - - cpu divider ratio can be configured via these 4 bits individually. - - - b y te 16 - pci divider ratio can be configured via these 4 bits individually. - - - see table: divider ratio combination table b y te 18 b y te 17 - - - see table: 7-steps skew programming table see table: 7-steps skew programming table - - - - - reserved reserved reserved see table: divider ratio combination table see table: divider ratio combination table reserved reserved reserved reserved reserved reserved reserved reserved
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 10 i 2 c table: group skew control register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 pci_skw3 rw 0 bit 2 pci_skw2 rw 0 bit 1 pci_skw1 rw 0 bit 0 pci_skw0 rw 0 i 2 c table: slew rate control register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 i 2 c table: slew rate control register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 i 2 c table: slew rate control register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 i 2 c table: slew rate control register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 - pci skew control - - - b y te 19 b y te 20 b y te 21 b y te 22 b y te 23 see table: 7-steps skew programming table reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 11 i 2 c table: slew rate control register pin # nam e control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 i 2 c table: test byte register test t yp epwd bit 7 rw 0 bit 6 rw 0 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 0 b y te 24 b y te 25 - - - - ics only test - - - - ics only test ics only test ics only test ics only test test function ics only test ics only test ics only test reserved reserved reserved reserved reserved test result reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 12 absolute max electrical characteristics - input/supply/common output parameters t a = -40 to 85c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v input high current i ih v in = v d d -5 5 ua i il1 v in = 0 v; inputs with no pull- u p resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua low threshold input high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v low threshold input low volta g e v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v operating supply current i dd3.3op 3.3 v +/-5%, full load 350 500 ma all diff p airs driven 70 ma all differential p airs tri-stated 12 ma in p ut fre q uenc y 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l pin 7nh1 c in logic inputs 5 pf 1 c ou t output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1,2 modulation fre q uenc y trian g ular modulation 30 33 khz 1 tdrive_pd# cpu output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v olsmbus @ i pullup 0.4 v 1 c urrent sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 see timing diagrams for timing requirements. 3 input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm accuracy on pll outputs. input low current powerdown current i dd3.3pd input capacitance 1 symbol parameter min typ max units vdd_a 3.3v core supply voltage v dd + 0.5v v vdd_in 3.3v logic input supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp -40 85 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v ja thermal resistance junction to ambient 57.4 c/w jc thermal resistance junction to case 38.8 c/w
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 13 electrical characteristics - cpu 0.7v current mode differential pair t a = -40 to 85c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max volta g evovs 1150 1 min volta g e vuds -300 1 crossin g volta g e (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 lon g accurac y ppm see tperiod min-max values -300 300 ppm 1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz spread 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz spread 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz spread 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz s p read 7.4978 5.4000 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 cpu (1:0) v t = 50% 100 ps 1 skew t sk4 cpu (1:0) to cpu_itp, v t = 50% 150 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 85 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout p ut is at 14.31818mhz t absmin absolute min period statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv average period tperiod
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 14 electrical characteristics - src 0.7v current mode differential pair t a = -40 to 85c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 850 1 volta g e low vlow -150 150 1 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossing voltage (abs) vcross(abs) 250 350 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1 lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 absolute min p eriod tabsmin 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 src(7:0), v t = 50% 250 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all long term accuracy and clock period specifications are guaranteed assuming that refoutput is at 14.31818mhz mv measurement on sin g le ended signal using absolute value. mv average period tperiod statistical measurement on sin g le ended signal using oscilloscope
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 15 electrical characteristics - pciclk/pciclk_f t a = -40 to 85c; v dd = 3.3 v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 33.33mhz out p ut nominal 29.99100 30.00900 ns 2 33.33mhz out p ut s p read 29.99100 30.15980 ns 2 33.33mhz output nominal 29.49100 30.50900 ns 2 33.33mhz out p ut s p read 29.49100 30.65980 ns 2 clk high time t h1 12 n/a ns 1 clock low time t l1 12 n/a ns 1 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 500 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout p ut is at 14.31818mhz output low current i ol absolute min/max clock period t abs clock period t period output high current i oh electrical characteristics - usb_48mhz t a = -40 to 85c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp m see t p eriod min-max values -100 100 pp m1,2 clock p eriod t p eriod 48.0000mhz out p ut nominal 20.82570 20.83400 ns 2 absolute min/max clock p eriod t abs nominal 20.48125 21.18542 ns 2 clk high time t h1 8.094 10.036 ns 1 clock low time t l1 7.694 9.836 ns 1 v oh @ min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma ed g e rate risin g ed g e rate 1 2 v/ns 1 edge rate falling edge rate 1 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 11.432 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 11.332 ns 1 duty cycle d t1 v t = 1.5 v 45 48 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout p ut is at 14.31818mhz output low current i ol output high current i oh
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 16 electrical characteristics - dot, 96mhz 0.7v current mode differential pair t a = -40 to 85c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source out p ut im p edance zo v o = v x 3000 ? 1 volta g e hi g hvhi g h6608501 volta g e low vlow -150 150 1 max volta g e vovs 1150 1 min volta g evuds -300 1 crossing voltage ( abs ) vcross(abs) 250 550 mv 1 crossing voltage ( var ) d-vcross variation of crossing over all ed g es 140 mv 1 long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 average period tperiod 96.00mhz nominal 10.4135 10.4198 ns 2 absolute min period tabsmin 96.00mhz nominal 10.1635 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 250 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout p ut is at 14.31818mhz measurement on single ended signal using mv statistical measurement on single ended signal mv electrical characteristics - ref-14.318mhz t a = -40 to 85c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1 clock period t p eriod 14.318mhz output nominal 69.82700 69.85500 ns 1 absolute min/max clock period t abs nominal 68.82033 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 skew t sk1 v t = 1.5 v 500 ps 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1 1 guaranteed b y desi g n, not 100% tested in production.
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 17 test clarification table comments fs_c/test _sel hw pin fs_b/test _mode hw pin test entry bit b6b6 ref/n or hi-z b6b7 output 0x0xnormal 10x0hi-z 10x1ref/n 11x0ref/n 11x1ref/n 0x10hi-z 0x11ref/n b6b6: 1= enter test mode, default = 0 (normal operation) b6b7: 1= ref/n, default = 0 (hi-z) hw s w fs_c/test_sel is a 3-level latched input. o power-up w/ v >= 2.0v to select test o power-up w/ v < 2.0v to have pin function as fs_c. when pin is fs_c, vih_fs and vil_fs levels apply. fs_b/test_mode is a low-threshold input o vih_fs and vil_fs levels apply. o test_mode is a real time input test_sel can be invoked after power up through smbus b6b6. o if test is selected by b6b6, only b6b7 controls test_mode. the fs_b/test_mode pin is not used. power must be cycled to exit test.
idt tm programmable timing control hub tm for intel systems 1408a?01/25/10 ICS9E4101 programmable timing control hub tm for intel systems 18 min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a0808 variations min max min max 56 18.31 18.55 .720 .730 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d (inch) symbol see variations see variations index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l ordering information 9e4101 y filft example: designation for tape and reel packaging lead free, rohs compliant industrial temperature range package type f = ssop revision designator (will not correlate with datasheet revision) device type xxxx y f i lf t
ICS9E4101 programmable timing control hub tm for intel systems 19 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2009 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 10/25/07 initial release - 0.2 07/11/08 corrected operating temperature range on "absolute max" electrical characteristics table. 12 0.3 10/06/08 corrected t y po on orderin g information. 19 0.4 01/07/09 removed "advanced information" from document header. various 0.5 02/17/09 added thermal chars. 12 a 01/25/10 released to final. updated document template.

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